1. Field of the Invention
The present invention relates to an image processing apparatus, and a control method for the image processing apparatus.
2. Description of the Related Art
A programmable logic device stores circuit configuration data relating to electronic components constituting a circuit and wirings in an external storage device (e.g., a read-only memory (ROM), a flash memory). Then, the programmable logic device is an integrated circuit that can realize arbitrary logic circuits by loading circuit configuration data as the need arises, and changing a connection state among a plurality of embedded logic elements in accordance with the loaded circuit configuration data.
A typical programmable logic device includes a field programmable gate array (FPGA). In recent years, the needs for processing suited to types and statuses of images have been increasing, along with sophistication of image information processing. In such cases, it is conceivable that the above-described needs can be satisfied by mounting the FPGA in processing apparatuses, and generating circuit configuration data optimized based on required specifications for each processing apparatus.
Further, Japanese Patent Application Laid-Open No. 2007-179358 (hereinafter Japan '358) discusses a technique, when a user wants to switch between a plurality of hardware functions as circumstances demand in one processing apparatus, for selecting and reading out circuit configuration data depending on processing, out of a plurality of circuit configuration data that has been previously stored in an external memory. When the hardware functions of the image processing apparatus are switched using the technique discussed in Japan '358, the circuit configuration data will be loaded, register setting will be performed on the configured circuit on the FPGA, and after that, image processing will be started.
When the hardware functions of the image processing apparatus are switched between the processing using the technique discussed in Japan '358, a time required for switching is a total of a time required for loading the circuit configuration data and rasterizing the circuit configuration data on the FPGA, and a time required for register setting on the configured circuit (register setting time). Therefore, there is a problem that it takes a long time to perform the processing, and thus performance of the entire processing apparatus would be eventually degraded.
In order to reduce the register setting time, a method is conceivable for preparing circuit configuration data sets each having necessary register setting value as an initial value, for all of necessary register setting values, using the technique discussed in Japan '358. However, in this method, it is necessary to store previously a huge amount of the circuit configuration data, and required memory capacity would become larger. Thus, the method is not preferable.
As described above, there are various problems in the image processing apparatus having the programmable logic device.